Low-power high-performance VLSI design

TopicLeading institutions, researchers & key papers

This cluster of papers focuses on the design and optimization of low-power VLSI circuits, with an emphasis on techniques such as approximate computing, subthreshold operation, and leakage reduction. The papers also address challenges related to process variation, statistical timing analysis, and energy efficiency in CMOS technology at the nanometer scale.

Works

IDs:OpenAlex

How has Low-power high-performance VLSI design's publication output changed over time?

ScholarIQpublication output · 2004–2023

Output grew0% over the shown period — from 1 works in 2004 to 1 in 2023.

2004200720082009201120122015202120222023

What are the most-cited papers on Low-power high-performance VLSI design?

ScholarIQmost cited works

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, S. Ohbayashi, Y. Oda, Keiichi Usui, Takeshi Kawamura, Nobuo Tsuboi, T. Iwasaki, Kazuhito Hashimoto, Hiroshi Makino, Hirofumi Shinohara

2008114 Citations

Designing Asynchronous Circuits using NULL Convention Logic (NCL)

Scott C. Smith, Jia Di

Synthesis lectures on digital circuits and systems. 2009103 CitationsOPEN ACCESS

Optimization of NULL convention self-timed circuits

Scott C. Smith, Ronald F. DeMara, J.S. Yuan, D. Ferguson, David Lamb

S139392130. 200498 CitationsOPEN ACCESS

Uncle - An RTL Approach to Asynchronous Design

R.B. Reese, Scott C. Smith, Mitchell A. Thornton

201275 Citations

Delay-insensitive gate-level pipelining

Scott C. Smith, Ronald F. DeMara, J.S. Yuan, M. Hagedorn, D. Ferguson